Publications
Fidel: Reconstructing private training samples from weight updates in federated learning, D Enthoven, Z Al-Ars, International Conference on Internet of Things: Systems, Management, 2022
SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs, S Park, H Kim, T Ahmad, N Ahmed, Z Al-Ars, HP Hofstee, Y Kim, J Lee, 2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2022
Memory-Disaggregated In-Memory Object Store Framework for Big Data Applications, R Abrahamse, A Hadnagy, Z Al-Ars, IEEE International Parallel and Distributed Processing Symposium, 2022
WhiskEras 2.0: Fast and Accurate Whisker Tracking in Rodents, P Arvanitis, JHLF Betting, LWJ Bosman, Z Al-Ars, C Strydis, Embedded Computer Systems: Architectures, Modeling, and Simulation: 21st, 2022
Benchmarking Apache Arrow Flight-A wire-speed protocol for data transfer, querying and microservices, T Ahmad, Z Al-Ars, Benchmarking in the Data Center: Expanding to the Cloud, 1-10, 2022
BioDynaMo: a modular platform for high-performance agent-based simulation, L Breitwieser, A Hesam, J De Montigny, V Vavourakis, A Iosif, J Jennings, et al., Bioinformatics 38 (2), 453-460, 2022
Efficient decomposition of unitary matrices in quantum circuit compilers, AM Krol, A Sarkar, I Ashraf, Z Al-Ars, K Bertels. Applied Sciences 12 (2), 759, 2022
Palda: Public Dataset and Algorithms for Facial Imaging and Diagnosis of Neurological Disorders, N Sourlos, W Amerika, BC Jacobs, S de Bruijn, Z Al-Ars, Available at SSRN 4017045, 2022
WisecondorFF: Improved fetal aneuploidy detection from shallow WGS through fragment length analysis, T Mokveld, Z Al-Ars, EA Sistermans, M Reinders, Diagnostics 12 (1), 59, 2022
Tens of gigabytes per second JSON-to-Arrow conversion with FPGA accelerators, J Peltenburg, Á Hadnagy, M Brobbel, R Morrow, Z Al-Ars, International Conference on Field-Programmable Technology (ICFPT), 1-9, 2021
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project, C Sau, C Rinaldi, L Pomante, F Palumbo, G Valente, T Fanni, M Martinez, et al., Microprocessors and Microsystems 87, 104350, 2021
QiBAM: approximate sub-string index search on quantum accelerators applied to DNA read alignment, A Sarkar, Z Al-Ars, CG Almudever, KLM Bertels, Electronics 10 (19), 2021
VC@ Scale: Scalable and high-performance variant calling on cluster environments, T Ahmad, Z Al Ars, HP Hofstee, GigaScience 10 (9), 2021
FPGA Acceleration of Zstd Compression Algorithm, J Chen, M Daverveldt, Z Al-Ars, IEEE International Parallel and Distributed Processing Symposium, 2021
Gpu acceleration of 3d agent-based biological simulations, A Hesam, L Breitwieser, F Rademakers, Z Al-Ars, IEEE International Parallel and Distributed Processing Symposium, 2021
FPGA acceleration for big data analytics: Challenges and opportunities, J Hoozemans, J Peltenburg, F Nonnemacher, A Hadnagy, Z Al-Ars, et al., IEEE Circuits and Systems Magazine 21 (2), 30-47, 2021
Generating high-performance FPGA accelerator designs for big data analytics with Fletcher and Apache Arrow, J Peltenburg, J van Straten, M Brobbel, Z Al-Ars, HP Hofstee, Journal of Signal Processing Systems 93, 565-586, 2021
QuASeR: Quantum Accelerated de novo DNA sequence reconstruction, A Sarkar, Z Al-Ars, K Bertels, Plos one 16 (4), e0249850, 2021
Estimating algorithmic information using quantum computing for genomics applications, A Sarkar, Z Al-Ars, K Bertels, Applied Sciences, 11 (6), 2696, 2021
Energy Efficient Multistandard Decompressor ASIP, J Hoozemans, K Tervo, P Jaaskelainen, Z Al-Ars, International Conference on Computing and Data Engineering, 14-19, 2021
An attention module for convolutional neural networks, B Zhu, P Hofstee, J Lee, Z Al-Ars, Artificial Neural Networks and Machine Learning–ICANN, 2021
An overview of federated deep learning privacy attacks and defensive strategies, D Enthoven, Z Al-Ars, in “Federated Learning Systems: Towards Next-Generation AI”, 173-196, 2021
CHOP: Haplotype-aware path indexing in population graphs, T Mokveld, J Linthorst, Z Al-Ars, H Holstege, M Reinders, Genome Biology 21 (1), 2020
REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution, Z Baozhou, Z Al-Ars, HP Hofstee, IEEE Access, 2020
GPU acceleration of Darwin read overlapper for de novo assembly of long DNA reads, N Ahmed, TD Qiu, K Bertels, Z Al-Ars, BMC bioinformatics 21 (13), 2020
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project, L Pomante, F Palumbo, C Rinaldi, G Valente, C Sau, T Fanni, 23rd Euromicro Conference on Digital System Design (DSD), 378-385, 2020
NASB: Neural Architecture Search for Binary Convolutional Neural Networks, B Zhu, Z Al-Ars, HP Hofstee, International Joint Conference on Neural Networks (IJCNN), 2020
Flexhh: A flexible hardware library for hodgkin-huxley-based neural simulations, R Miedema, G Smaragdos, M Negrello, Z Al-Ars, M Möller, C Strydis, IEEE Access, 2020
Tydi: an open specification for complex data structures over hardware streams, J Peltenburg, M Brobbel, J Van Straten, Z Al-Ars, P Hofstee, IEEE Micro, 2020
ArrowSAM: In-Memory Genomics Data Processing Using Apache Arrow, T Ahmad, N Ahmed, J Peltenburg, Z Al-Ars, International Conference on Computer Applications & Information, 2020
Parallelization of Variable Rate Decompression through Metadata, L Noordsij, S van der Vlugt, MA Bamakhrama, Z Al-Ars, P Lindstrom, International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2020
Stairway to Abstraction: an Iterative Algorithm for Whisker Detection in Video Frames, JHLF Betting, V Romano, LWJ Bosman, Z Al-Ars, CI De Zeeuw, C Strydis, Latin American Symposium on Circuits & Systems (LASCAS), 2020
Synthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible Neurosimulations, R Miedema, G Smaragdos, M Negrello, Z Al-Ars, M Möller, C Strydis, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
Efficient GPU Acceleration for Computing Maximal Exact Matches in Long DNA Reads, N Ahmed, K Bertels, Z Al-Ars, International Conference on Bioscience, Biochemistry and Bioinformatics, 2020
WhiskEras: A New Algorithm for Accurate Whisker Tracking, JH Betting, V Romano, Z Al-Ars, L Bosman, C Strydis, C De Zeeuw, Frontiers in Cellular Neuroscience 14, 2020
SparkRA: Enabling big data scalability for the GATK RNA-seq pipeline with apache spark, Z Al-Ars, S Wang, H Mushtaq, Genes 11 (1), 53, 2020
Exploring Complex Brain-Simulation Workloads on Multi-GPU Deployments, MA Vlag, G Smaragdos, Z Al-Ars, C Strydis, ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 53, 2019
SparkGA2: Production-quality memory-efficient Apache Spark based genome analysis framework, H Mushtaq, N Ahmed, Z Al-Ars, PloS one, 2019
GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data, N Ahmed, J Lévy, S Ren, H Mushtaq, K Bertels, Z Al-Ars, BMC bioinformatics 20 (1), 520, 2019
Early DNA Analysis Using Incomplete DNA Datasets, Z Al-Ars, A Nauman, KLM Bertels, US Patent App. 16/348, 171, 2019
An algorithm for DNA read alignment on quantum accelerators, A Sarkar, Z Al-Ars, CG Almudever, K Bertelsar, Xiv preprint arXiv: 1909.05563, 2019
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow, J Peltenburg, J van Straten, L Wijtemans, L van Leeuwen, Z Al-Ars, et. al, 29th International Conference on Field Programmable Logic, 2019
Refine and Recycle: A Method to Increase Decompression Parallelism, J Fang, J Chen, J Lee, Z Al-Ars, HP Hofstee, 2019 IEEE 30th International Conference on Application-specific Systems, 2019
The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems, Z Al-Ars, T Basten, A de Beer, M Geilen, D Goswami, P Jääskeläinen, et. al, Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model, J Fang, J Chen, J Lee, Z Al-Ars, HP Hofstee, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom, 2019
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow, J Peltenburg, J van Straten, M Brobbel, HP Hofstee, Z Al-Ars, International Symposium on Applied Reconfigurable Computing, 32-47, 2019
GPU accelerated sequence alignment with traceback for GATK HaplotypeCaller, S Ren, N Ahmed, K Bertels, Z Al-Ars, BMC genomics 20 (2), 184, 2019
Diminished-1 Fermat Number Transform for Integer Convolutional Neural Networks, Z Baozhou, N Ahmed, J Peltenburg, K Bertels, Z Al-Ars, 2019 IEEE 4th International Conference on Big Data Analytics (ICBDA), 47-52, 2019
SparkJNI: A Toolchain for Hardware Accelerated Big Data Apache Spark, TA Voicu, Z Al-Ars, 2019 IEEE 4th International Conference on Big Data Analytics (ICBDA), 152-157, 2019
An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM, L van Dam, J Peltenburg, Z Al-Ars, HP Hofstee, Proceedings of the Conference for Next Generation Arithmetic, 2019
ArrowSAM: In-Memory Genomics Data Processing through Apache Arrow Framework, T Ahmad, J Peltenburg, N Ahmed, Z Al Ars, bioRxiv, 741843, 2019
Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS, M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars, Journal of Electronic Testing, 1-13, 2019
Frame-based programming, stream-based processing for medical image processing applications, J Hoozemans, R De Jong, S Van Der Vlugt, J Van Straten, UK Elango, et al, Journal of signal processing systems 91 (1), 47-59, 2019
ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA, J Hoozemans, J van Straten, T Viitanen, A Tervo, J Kadlec, Z Al-Ars, Journal of signal processing systems 91 (1), 61-73, 2019
ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications, Z Al-Ars, S van der Vlugt, P Jääskeläinen, F van der LindenJournal of Signal Processing Systems 91 (1), 1-7, 2019
An Efficient GPU-Based de Bruijn Graph Construction Algorithm for Micro-Assembly, S Ren, N Ahmed, K Bertels, Z Al-Ars, 2018 IEEE 18th International Conference on Bioinformatics and Bioengineering, 2018
Comparative analysis of system-level acceleration techniques in bioinformatics: A case study of accelerating the smith-waterman algorithm for bwa-mem, EJ Houtgast, VM Sima, K Bertels, Z Al-Ars, 2018 IEEE 18th International Conference on Bioinformatics and Bioengineering, 2018
A high-bandwidth Snappy decompressor in reconfigurable logic: work-in-progress, J Fang, J Chen, Z Al-Ars, P Hofstee, J Hidders, Proceedings of the International Conference on Hardware/Software Codesign, 2018
Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing, M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars, 2018 IEEE East-West Design & Test Symposium (EWDTS), 1-6, 2018
Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths, EJ Houtgast, VM Sima, K Bertels, Z Al-Ars, Computational biology and chemistry, 2018
Porting and Benchmarking of BWAKIT Pipeline on OpenPOWER Architecture, N Kathiresan, R Al-Ali, P Jithesh, G Narayanasamy, Z Al-Ars, International Conference on High Performance Computing, 402-410, 2018
Evaluating auto-adaptation methods for fine-grained adaptable processors, J Hoozemans, J van Straten, Z Al-Ars, S Wong, International Conference on Architecture of Computing Systems, 255-268, 2018
A matrix-multiply unit for posits in reconfigurable logic leveraging (open) CAPI, J Chen, Z Al-Ars, HP Hofstee, Proceedings of the Conference for Next Generation Arithmetic, 2018
An industrial case study of low cost adaptive voltage scaling using delay test patterns, M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018
Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling, M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 289-292, 2018
GPU-based stochastic-gradient optimization for non-rigid medical image registration in time-critical applications, P Bhosale, M Staring, Z Al-Ars, FF Berendsen, Medical Imaging 2018: Image Processing, 2018
Efficient acceleration of the pair-hmms forward algorithm for gatk haplotypecaller on graphics processing units, S Ren, K Bertels, Z Al-Ars, Evolutionary Bioinformatics 14, 2018
CHOP: Haplotype-aware path indexing in population graphs, TO Mokveld, J Linthorst, Z Al-Ars, M Reinders, bioRxiv, 305268, 2018
GPU accelerated API for alignment of genomics sequencing data, N Ahmed, H Mushtaq, K Bertels, Z Al-Ars, 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017
BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations, G Smaragdos, G Chatzikonstantis, R Kukreja, H Sidiropoulos, et. al, Journal of neural engineering 14 (6), 2017
High performance streaming Smith-Waterman implementation with implicit synchronization on Intel FPGA using OpenCL, E Houtgast, VM Sima, Z Al-Ars, 2017 IEEE 17th International Conference on Bioinformatics and Bioengineering, 2017
GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization, S Ren, K Bertels, Z Al-Ars, 2017 IEEE 17th International Conference on Bioinformatics and Bioengineering, 2017
Predictive Genome Analysis Using Partial DNA Sequencing Data, N Ahmed, K Bertels, Z Al-Ars, 2017 IEEE 17th International Conference on Bioinformatics and Bioengineering, 2017
Streaming Distributed DNA Sequence Alignment Using Apache Spark, H Mushtaq, N Ahmed, Z Al-Ars, 2017 IEEE 17th International Conference on Bioinformatics and Bioengineering, 2017
Sparkga: A spark framework for cost effective, fast and accurate dna analysis at scale, H Mushtaq, F Liu, C Costa, G Liu, P Hofstee, Z Al-Ars, Proceedings of the 8th ACM International Conference on Bioinformatics, 2017
Towards real-time whisker tracking in rodents for studying sensorimotor disorders, Y Ma, PR Geethakumari, G Smaragdos, S Lindeman, V Romano, et. al, 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Pushing big data into accelerators: Can the JVM saturate our hardware?, J Peltenburg, A Hesam, Z Al-Ars, International Conference on High Performance Computing, 220-236, 2017
Using transition fault test patterns for cost effective offline performance estimation, M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars, 2017 12th International Conference on Design & Technology of Integrated, 2017
VLIW-based FPGA computation fabric with streaming memory hierarchy for medical imaging applications, J Hoozemans, R Heij, J van Straten, Z Al-Ars, International Symposium on Applied Reconfigurable Computing, 36-43, 2017
An efficient gpuaccelerated implementation of genomic short read mapping with bwamem, EJ Houtgast, VM Sima, K Bertels, Z AlArs, ACM SIGARCH Computer Architecture News 44 (4), 38-43, 2017
Transition Fault Testing for Offline Adaptive Voltage Scaling, M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars, ITC, 2017
Industrial approaches for performance evaluation using on-chip monitors, M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars, 2016 11th International Design & Test Symposium (IDT), 210-215, 2016
Maximizing systolic array efficiency to accelerate the PairHMM forward algorithm, J Peltenburg, S Ren, Z Al-Ars, 2016 IEEE International Conference on Bioinformatics and Biomedicine, 2016
Exploration of alternative GPU implementations of the pair-HMMs forward algorithm, S Ren, K Bertel, Z Al-Ars, 2016 IEEE International Conference on Bioinformatics and Biomedicine, 2016
A comparison of seed-and-extend techniques in modern DNA read alignment algorithms, N Ahmed, K Bertels, Z Al-Ars, 2016 IEEE International Conference on Bioinformatics and Biomedicine, 2016
Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms, EJ Houtgast, VM Sima, G Marchiori, K Bertels, Z Al-Ars, 2016 International Conference on ReConFigurable Computing and FPGAs, 2016
Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms, EJ Houtgast, VM Sima, G Marchiori, K Bertels, Z Al-Ars, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom, 2016
Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector, V Kritchallo, B Braithwaite, E Vermij, K Bertels, Z Al-Ars, International Conference on Architecture of Computing Systems, 251-262, 2016
GPU-accelerated BWA-MEM genomic mapping algorithm using adaptive load balancing, EJ Houtgast, VM Sima, K Bertels, Z Al-Ars, International Conference on Architecture of Computing Systems, 130-142, 2016
Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector, K Bertels, Z Al-Ars, 29th International Conference on Architecture of Computing Systems, 2016
Challenges of using on-chip performance monitors for process and environmental variation compensation, M Zandrahimi, Z Al-Ars, P Debaud, A Castillejo, 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Fidelity slider: a user-defined method to trade off accuracy for performance in canny edge detector, V Kritchallo, E Vermij, K Bertels, Z Al-Ars, 2nd Workshop On Approximate Computing, HiPEAC, 2016
Computational Challenges of Next Generation Sequencing Pipelines Using Heterogeneous Systems, EJ Houtgast, VM Sima, K Bertels, Z Al-Ars, 12th International Summer School on Advanced Computer Architecture, 2016
Heterogeneous Hardware Accelerators with Hybrid Interconnect: an Automated Design Approach, C Pham-Quoc, I Ashraf, Z Al-Ars, K Bertels, 2015 International Conference on Advanced Computing and Applications, 2015
Cluster-based Apache Spark implementation of the GATK DNA analysis pipeline, H Mushtaq, Z Al-Ars, IEEE International Conference on Bioinformatics and Biomedicine, 2015
FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis, S Ren, VM Sima, Z Al-Ars, IEEE International Conference on Bioinformatics and Biomedicine, 2015
Heterogeneous hardware/software acceleration of the BWA-MEM DNA alignment algorithm, N Ahmed, VM Sima, E Houtgast, K Bertels, Z Al-Ars, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 240-246, 2015
Calculation of worst-case execution time for multicore processors using deterministic execution, H Mushtaq, Z Al-Ars, K Bertels, 25th International Workshop on Power and Timing Modeling, Optimization, 2015
Using VLIW softcore processors for image processing applications, J Hoozemans, S Wong, Z Al-Ars, International Conference on Embedded Computer Systems, 2015
An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm, EJ Houtgast, VM Sima, K Bertels, Z Al-Ars, International Conference on Embedded Computer Systems, 2015
Accelerating complex brain-model simulations on GPU platforms, HA Du Nguyen, Z Al-Ars, G Smaragdos, C Strydis, Design, Automation & Test in Europe Conference & Exhibition (DATE), 974-979, 2015
Analysis of RNAseq datasets from a comparative infectious disease zebrafish model using GeneTiles bioinformatics, WJ Veneman, J de Sonneville, KJ van der Kolk, A Ordas, Z Al-Ars, Immunogenetics 67 (3), 135-147, 2015
Scalability Potential of BWA DNA Mapping Algorithm on Apache Spark, Z Al-Ars, H Mushtaq, SIMBig, 85-88, 2015
Generic march element based memory built-in self test, S Hamdioui, Z Al-Ars, GN Gaydadjiev, A Van de Goor, US Patent 8,910,001, 2014
Efficient and highly portable deterministic multithreading (DetLock), H Mushtaq, Z Al-Ars, K Bertels, Computing 96 (12), 1131-1147, 2014
A survey on low-power techniques for single and multicore systems, M Zandrahimi, Z Al-Ars, Proceedings of the 3rd International Conference on Context-Aware Systems, 2014
Automated hybrid interconnect design for fpga accelerators using data communication profiling, C Pham-Quoc, Z Al-Ars, K Bertels, IEEE International Parallel & Distributed Processing Symposium, 2014
Integrated Approach to Whole Genome Diagnostics, Z Al-Ars, K Bertels, E Cuppen, Netherlands Bioinformatics Conference, 2014
Fault tolerance on multicore processors using deterministic multithreading, H Mushtaq, Z Al-Ars, K Bertels, 8th IEEE Design and Test Symposium, 1-6, 2013
Accurate and efficient identification of worst-case execution time for multicore processors: A survey, H Mushtaq, Z Al-Ars, K Bertels, 8th IEEE Design and Test Symposium, 1-6, 2013
Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms, S Majzoub, Z Alars, S Hamdioui, 8th IEEE Design and Test Symposium, 1-6, 2013
Heterogeneous hardware accelerator architecture for streaming image processing, C Pham-Quoc, Z Al-Ars, K Bertels2013 International Conference on Advanced Technologies for Communications, 2013
Heterogeneous hardware accelerators interconnect: An overview, C Pham-Quoc, Z Al-Ars, K Bertels, NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), 189-197, 2013
Hybrid interconnect design for heterogeneous hardware accelerators, C Pham-Quoc, J Heisswolf, S Werner, Z Al-Ars, J Becker, K Bertels, Design, Automation & Test in Europe Conference & Exhibition (DATE), 843-846, 2013
Efficient software-based fault tolerance approach on multicore platforms, H Mushtaq, Z Al-Ars, K Bertels, Proceedings of the Conference on Design, Automation and Test in Europe, 921-926, 2013
Rule-based data communication optimization using quantitative communication profiling, CP Quoc, Z Al-Ars, K Bertels, 2012 International Conference on Field-Programmable Technology, 104-108, 2012
A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems, C Pham-Quoc, Z Al-Ars, K Bertels, 2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
DetLock: portable and efficient deterministic execution for shared memory multicore systems, H Mushtaq, Z Al-Ars, K Bertels, 2012 SC Companion: High Performance Computing, Networking Storage, 2012
A user-level library for fault tolerance on shared memory multicore systems, H Mushtaq, Z Al-Ars, K Bertels, IEEE 15th International Symposium on Design and Diagnostics, 2012
4-D parity codes for soft error correction in aerospace applications, M Imran, Z Al-Ars, GN Gaydadjiev, IEEE 6th International Design and Test Workshop (IDT), 104-109, 2011
Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems, H Mushtaq, Z Al-Ars, K Bertels, IEEE 6th International Design and Test Workshop (IDT), 12-17, 2011
DOPA: GPU-based protein alignment using database and memory access optimizations, L Hasan, M Kentie, Z Al-Ars, BMC research notes 4 (1), 261, 2011
Testing for parasitic memory effect in SRAMs, S Irobi, Z Al-Ars, S Hamdioui, C Thibeault, Asian Test Symposium, 407-412, 2011
A New Test Paradigm for Semiconductor Memories in the Nano-Era, S Hamdioui, V Krishnaswami, IS Irobi, Z Al-Ars, Asian Test Symposium, 347-352, 2011
An overview of hardware-based acceleration of biological sequence alignment, L Hasan, Z Al-Ars, Computational Biology and Applied Bioinformatics, 187-202, 2011
GPU-accelerated protein sequence alignment, L Hasan, M Kentie, Z Al-Ars, Annual International Conference of the IEEE Engineering in Medicine, 2011
Memory test optimization for parasitic bit line coupling in srams, S Irobi, Z Al-Ars, S Hamdioui, Sixteenth IEEE European Test Symposium, 205-205, 2011
Influence of parasitic memory effect on single-cell faults in SRAMs, S Irobi, Z Al-Ars, S Hamdioui, M Renovell, 14th IEEE International Symposium on Design and Diagnostics, 2011
Performance and bandwidth optimization for biological sequence alignment, L Hasan, Z Al-Ars, M Taouil, K Bertels, 5th International Design and Test Workshop, 155-160, 2010
Parasitic memory effect in cmos srams, S Irobi, Z Al-Ars, M Renovell, 5th International Design and Test Workshop, 134-139, 2010
Detecting memory faults in the presence of bit line coupling in SRAM devices, S Irobi, Z Al-Ars, S Hamdioui, IEEE International Test Conference, 1-10, 2010
Indexys, a logical step beyond genesys, A Eckel, P Milbredt, Z Al-Ars, S Schneele, B Vermeulen, G Csertán, International Conference on Computer Safety, Reliability, and Security, 431-451, 2010
High performance and resource efficient biological sequence alignment, L Hasan, Z Al-Ars, M Taouil, 2010 Annual International Conference of the IEEE Engineering in Medicine, 2010
Bit line coupling memory tests for single-cell fails in SRAMs, S Irobi, Z Al-Ars, S Hamdioui, 28th VLSI Test Symposium (VTS), 27-32, 2010
Fault Diagnosis Using Test Primitives in Random Access Memories, Z Al-Ars, S Hamdioui, Asian Test Symposium, 403-408, 2009
New algorithms for address decoder delay faults and bit line imbalance faults, AJ Van de Goor, S Hamdioui, GN Gaydadjiev, Z Al-Ars, Asian Test Symposium, 391-396, 2009
Non-algorithmic stress optimization using simulation for DRAMs, Z Al-Ars, S Hamdioui, 4th International Design and Test Workshop (IDT), 1-6, 2009
Worst-Case Bit Line Coupling Backgrounds for Open Defects in SRAM Cells, S Irobi, Z Al-Ars, 20th Annual Workshop on Circuits, Systems and Signal Processing, 2009
Performance comparison between linear rve and linear systolic array implementations of the smith-waterman algorithm, L Hasan, Z Al-Ars, Proc. 20th Annual Workshop on Circuits, Systems and Signal Processing, 2009
An efficient and high performance linear recursive variable expansion implementation of the smith-waterman algorithm, L Hasan, Z Al-Ars, 2009 Annual International Conference of the IEEE Engineering in Medicine, 2009
Improving soft error correction capability of 4-d parity codes, M Imran, Z Al-Ars, GN Gaydadjiev, 14th IEEE European Test Symposium, 2009
Scan more with memory scan test, S Hamdioui, Z Al-Ars, 4th International Conference on Design & Technology of Integrated Systems, 2009
Efficient tests and DFT for RAM address decoder delay faults, S Hamdioui, Z Al-Ars, 3rd International Design and Test Workshop, 225-230, 2008
Evaluation of SRAM faulty behavior under bit line coupling, Z Al-Ars, S Hamdioui, 3rd International Design and Test Workshop, 231-235, 2008
Hardware implementation of the Smith-Waterman algorithm using recursive variable expansion, L Hasan, Z Al-Ars, Z Nawaz, K Bertels, 3rd International Design and Test Workshop, 135-140, 2008
Automating defects simulation and fault modeling for SRAMs, S Di Carlo, P Prinetto, A Scionti, Z Al-Ars, 2008 IEEE International High Level Design Validation and Test Workshop, 169-176, 2008
BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs, S Hamdioui, Z Al-Ars, J Jimenez, J Calero, 2008 2nd International Conference on Signals, Circuits and Systems, 1-6, 2008
A Novel Approach for Accelerating the Smith-Waterman Algorithm using Recursive Variable Expansion, L Hasan, Z Al-Ars, Z Nawaz, Proc. 19th Annual Workshop on Circuits, Systems and Signal Processing, 2008
Defect oriented testing of the strap problem under process variations in DRAMs, Z Al-Ars, S Hamdioui, AJ van de Goor, G Mueller, IEEE International Test Conference, 1-10, 2008
Acceleration of smith-waterman using recursive variable expansion, Z Nawaz, M Shabbir, Z Al-Ars, K Bertels, 11th EUROMICRO Conference on Digital System Design Architectures, 2008
Test set development for cache memory in modern microprocessors, Z Al-Ars, S Hamdioui, G Gaydadjiev, S Vassiliadis, IEEE transactions on very large scale integration (VLSI) systems 16 (6), 725-732, 2008
Accurate profiling and acceleration evaluation of the Smith-Waterman algorithm using the MOLEN platform, L Hasan, Z Al-Ars, Proceedings of IADIS International Conference on Applied Computing, Algarve, 2008
Precise Identification of Memory Faults Using Electrical Simulation, Z Al-Ars, S Hamdioui, G Gaydadjiev, 2007 2nd International Design and Test Workshop, 3-8, 2007
An investigation on capacitive coupling in ram address decoders, S Hamdioui, Z Al-Ars, GN Gaydadjiev, AJ van de Goor, 2nd International Design and Test Workshop, 9-14, 2007
Design and implementation of reliable Wireless Sensor Networks-A case study in commuter trains, S Kootkar, Z Al-Ars, Proceedings of ProRISC workshop, 201-204, 2007
Performance Improvement of the Smith-Waterman Algorithm, L Hasan, Z Al-Ars, Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30, 2007
Automatic analysis of memory faulty behavior in defective memories, Z Al-Ars, S Hamdioui, 2007 International Conference on Design & Technology of Integrated Systems, 2007
Hardware acceleration of sequence alignment algorithms-an overview, L Hasan, Z Al-Ars, S Vassiliadis, 2007 International Conference on Design & Technology of Integrated Systems, 2007
PPM reduction on embedded memories in system on chip, S Hamdioui, Z Al-Ars, J Jimenez, J Calero, 12th IEEE European Test Symposium (ETS’07), 85-90, 2007
Optimizing test length for soft faults in DRAM devices, Z Al-Ars, S Hamdioui, G Gaydadjiev, 25th IEEE VLSI Test Symposium (VTS’07), 59-66, 2007
Manifestation of precharge faults in high speed DRAM devices, Z Al-Ars, S Hamdioui, G Gaydadjiev, IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-6, 2007
Influence of bit-line coupling and twisting on the faulty behavior of DRAMs, Z Al-Ars, S Hamdioui, AJ van de Goor, S Al-Harbi, IEEE Transactions on Computer-Aided Design of Integrated Circuits, 2006
DesignMap: capturing design knowledge in architectural practice, B Tunçer, Z Al-Ars, E Akar, J Beintema, S Sariyildiz, Conference Proceedings of the Joint International Conference on Construction, 2006
Using Linear Tests for Transient Faults in DRAMs, Z Al-Ars, S Hamdioui, G Gaydadjiev, Proc. IEEE International Design and Test Workshop, 2006
Comparison of Static and Dynamic Faults in 65nm Memory Technology, S Hamdioui, Z Al-ars, GN Gaydadjiev, S Vassiliadis, 2006
Opens and delay faults in cmos ram address decoders, S Hamdioui, Z Al-Ars, AJ Van de Goor, IEEE Transactions on Computers 55 (12), 1630-1639, 2006
DRAM-specific space of memory tests, Z Al-Ars, S Hamdioui, A Van De Goor, G Gaydadjiev, J Vollrath, IEEE International Test Conference, 1-10, 2006
Trends in tests and failure mechanisms in deep sub-micron technologies, S Hamdioui, Z Al-Ars, L Mhamdi, G Gaydadjiev, S Vassiliadis, International Conference on Design and Test of Integrated Systems, 2006
Bitline-coupled precharge faults and their detection in memory devices, Z Al-Ars, S Hamdioui, G Mueller, J Vollrath, Proc. European Test Symp. Digest of Papers, 2006
Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies, S Hamdioui, Z Al-Ars, G Gaydadjiev, JD Reyes, IEEE Proc. European Test Symposium Digest of Papers, 2006
Space of DRAM fault models and corresponding testing, Z Al-Ars, S Hamdioui, AJ van de Goor, Proceedings of the conference on Design, automation and test in Europe, 2006
Investigations of faulty DRAM behavior using electrical simulation versus an analytical approach, Z Al-Ars, S Hamdioui, J Vollrath, 14th Asian Test Symposium (ATS’05), 434-439, 2005
Impact of stresses on the fault coverage of memory tests, S Hamdioui, Z Al-Ars, AJ van de Goor, R Wadsworth, IEEE International Workshop on Memory Technology, Design, and Testing, 2005
Framework for fault analysis and test generation in drams, Z Al-Ars, S Hamdioui, G Mueller, AJ Goor, Proceedings of the conference on Design, Automation and Test in Europe, 2005
DRAM fault analysis and test generation, Z Al-Ars, 2005
Evaluation for intra-word faults in word-oriented rams, S Hamdioui, JD Reyes, Z Al-Ars, 13th Asian Test Symposium, 283-288, 2004
Influence of bit line twisting on the faulty behavior of DRAMs, Z Al-Ars, M Herzog, I Schanstra, AJ van de Goor, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004
The effectiveness of the scan test and its new variants, AJ van de Goor, S Hamdioui, Z Al-Ars, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004
Tests for address decoder delay faults in rams due to inter-gate opens, AJ van de Goor, S Hamdioui, Z Al-Ars, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., 146-151, 2004
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results, S Hamdioui, Z Al-Ars, AJ Van De Goor, M Rodgers, IEEE Transactions on Computer-Aided Design of Integrated Circuits, 2004
Effects of bit line coupling on the faulty behavior of DRAMs, Z Al-Ars, S Hamdioui, AJ van de Goor, 22nd IEEE VLSI Test Symposium, 117-122, 2004
Soft faults and the importance of stresses in memory testing, Z Al-Ars, AJ van de Goor, Proceedings of the conference on Design, automation and test in Europe, 2004
Task scheduling policies in general distributed systems: a survey and possibilities, M Shahsavari, MF Nadeem, SA Ostadzadeh, Z Al-Ars, K Bertels, 2004
Analyzing the impact of process variations on DRAM testing using border resistance traces, Z Al-Ars, AJ van de Goor, 2003
Test generation and optimization for DRAM cell defects using electrical simulation, Z Al-Ars, AJ van de Goor, IEEE Transactions on Computer-Aided Design of Integrated Circuits, 2003
Systematic memory test generation for DRAM defects causing two floating nodes, Z Al-Ars, AJ van de Goor, Records of the 2003 International Workshop on Memory Technology, Design and Testing, 2003
A fault primitive based analysis of linked faults in RAMs, Z Al-Ars, S Hamdioui, AJ van de Goor, Records of the 2003 International Workshop on Memory Technology, Design and Testing, 2003
March SL: A Test For All Static Linked Memory Faults, S Hamdioui, Z Al-Ars, AJ van de Goor, M Rodgers, Asian Test Symposium, 372-377, 2003
Dynamic faults in random-access-memories: Concept, fault models and tests, S Hamdioui, Z Al-Ars, AJ Van De Goor, M Rodgers, Journal of Electronic Testing 19 (2), 195-205, 2003
Static and dynamic behavior of memory cell array spot defects in embedded DRAMs, Z Al-Ars, AJ Van De Goor, IEEE Transactions on Computers 52 (3), 293-309, 2003
Optimizing stresses for testing DRAM cell defects using electrical simulation, Z Al-Ars, AJ van de Goor, J Braun, D Richter, Proceedings of the conference on Design, Automation and Test in Europe, 2003
DRAM specific approximation of the faulty behavior of cell defects, Z Al-Ars, AJ Van de GoorProceedings of the 11th Asian Test Symposium, 98-103, 2002
Approximating infinite dynamic behavior for DRAM cell defects, Z Al-Ars, AJ van de Goor, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 401-406, 2002
Testing static and dynamic faults in random access memories, S Hamdioui, Z Al-Ars, AJ Van de Goor, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 395-400, 2002
Modeling techniques and tests for partial faults in memory devices, Z Al-Ars, AJ van de Goor, Proceedings 2002 Design, Automation and Test in Europe, 2002
A memory specific notation for fault modeling, Z Al-Ars, AJ Van de Goor, J Braun, D Richter, Proceedings 10th Asian Test Symposium, 43-48, 2001
Simulation based analysis of temperature effect on the faulty behavior of embedded drams, Z Al-Ars, AJ van de Goor, J Braun, D Richter, Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 783-792, 2001
Transient faults in DRAMs: Concept, analysis and impact on tests, Z Al-Ars, AJ van de Goor, Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, 2001
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs, Z Al-Ars, AJ Van de Goor, Proceedings Design, Automation and Test in Europe. Conference and Exhibition, 2001
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs, Z Al-Ars, AJ Van De Goor, Proceedings of the Ninth Asian Test Symposium, 282-289, 2000
Functional Memory Faults: A Formal Notation and a Taxonomy, AJ Van de Goor, Z Al-Ars, VLSI Test Symposium 18, 281-289, 2000
Analysis of the space of functional fault models and its application to embedded drams, Z Al-Ars, Technical Report no. 1–68340–28 (1999)-07, CARDIT, 1999